1. Field of the Invention
The present invention relates to a semiconductor memory device such as DRAM, and, more particularly, to memory access control for a semiconductor memory device having a memory cell array including a redundant row. This application is based on Japanese Patent Application No. Hei 11-100623, the contents of which are incorporated herein by reference.
2. Description of Related Art Including Information Disclosed Under 37 CFR 1.97 and 37 CFR 1.98
A row decoder which selects a word line in a semiconductor memory device such as DRAM is typically constructed by a dynamic circuit because it has fewer elements than a static circuit and must switch word lines from one to another through a precharge period (where an external clock /RAS has a high level) in order to prevent information in the memory cells from being destroyed.
The xe2x80x9cstatic circuitxe2x80x9d here means the circuit structure that has a single PMOS transistor and NMOS transistor per single input of a plurality of row address predecode signal inputs and can set the input terminal of a buffer which activates or deactivates the associated word line to a high level or low level based on the associated predecode signal.
The xe2x80x9cdynamic circuitxe2x80x9d means the circuit structure that can set the input terminal of a buffer to a high level or low level by using means for precharging the input terminal of the buffer and means for discharging the input terminal in accordance with a plurality of row address predecode signal inputs. The logic level of the output of the static circuit is determined in accordance with the logic level of the input. By way of contrast, the logic level of the output of the dynamic circuit is determined in accordance with the logic level of the input immediately after precharging, but does not change according to the logic level of the input immediately once the circuit is discharged.
FIG. 9 shows the structure of the essential portion of a conventional semiconductor memory device of this type that is associated with word-line selection.
Referring to this figure, the semiconductor memory device comprises a precharge signal generator 200 which generates a precharge signal (PX2) for precharging a word line, a redundancy decision circuit 202 which determines whether or not to select a memory cell belonging to a redundant row, a row predecoder 204 which outputs address data for selecting one of normal row decoders 208-1 to 208-i based on an row address (XADD), a delay circuit 206 which delays the output of the row predecoder 204 by a predetermined time, and a redundant row decoder 210. The normal row decoders 208-1 to 208-i and redundant row decoder 210 are constructed by a dynamic circuit.
The output terminals of the normal row decoders 208-1 to 208-i are respectively connected to word lines 220-1 to 220-i, and the output terminal of the redundant row decoder 210 is connected to a word line 222. The operation of the thus constituted semiconductor memory device will be discussed with reference to FIG. 10. First, with every row address data or input address signal (XADD) set to a low level (non-selected state), the precharge signal PX2 of a low level is supplied to the individual normal row decoders 208-1 to 208-i and the redundant row decoder 210 until time t20, thereby precharging (rendering in a standby state) the output nodes of all the decoders or the word lines 220-1 to 220-i and 222 ((A) in FIG. 10). Even if the precharge signal PX2 becomes a high level at time t20, this low-voltage level is retained in each decoder.
When the row address is settled at time t21 ((B) in FIG. 10), the row predecoder 204 outputs a row predecode signal at time t22 ((D) in FIG. 10). This row predecode signal is delayed by a predetermined time Td in the delay circuit 206 and is input to the individual normal row decoders 208-1 to 208-i at time t24 ((E) in FIG. 10). In FIG. 10, xe2x80x9cTxe2x80x9d is the time needed for the redundancy decision circuit 202 to output a decision signal at time t23 from time t21 at which the row address has been settled.
The delay time Td of the delay circuit 206 in the conventional semiconductor memory device is set in such a way as to provide a sufficient time from the point of time when the redundancy decision circuit 202 has made a decision on as to whether or not to select a redundant row in the unillustrated memory cell array, i.e., time t23 at which the redundancy decision circuit 202 has output the redundancy decision signal, to time t24 at which the delay circuit 206 outputs the row predecode signal. Because of the use of a dynamic circuit for a row decoder, this row decoder is advantageous from the view point of the space as compared with a row decoder using a static circuit, but it cannot reset a word line once the word line is selected, i.e., the word line cannot be set back to a non-selected state. This therefore requires that the row predecode signal should be made to rise after the decision result of the redundancy decision circuit is output or the row predecode signal should be input to the target normal row decoder.
As the conventional semiconductor memory device is designed so as to raise the row predecode signal to select a normal row decoder after the decision result of the redundancy decision circuit is output, selection of a word line is delayed so that it takes time to read and output stored data.
Accordingly, it is an object of the present invention to provide a semiconductor memory device which is designed to speed up selection of a word line.
To achieve the above object, according to the first aspect of this invention, there is provided a semiconductor memory device having a memory cell array having a plurality of memory cells connected to respective word lines and data lines and having a redundant row of memory cells, for accessing any of the memory cells by changing an associated word line and associated data line from a standby state to an active state, which semiconductor memory device comprises a plurality of normal row decoders for decoding input row address data for specifying word lines when access is made to those of the memory cells which are other than the redundant row of memory cells, thereby selecting those word lines to which those memory cells that are other than the redundant row of memory cells are connected; a redundant row decoder for specifying that word line to which the redundant row of memory cells is connected when access is made to any memory cell which belongs to the redundant row; decision means for determining whether or not to select a memory cell belonging to the redundant row based on the input row address data and selecting the redundant row decoder at a time of selecting the memory cell belonging to the redundant row; and control means for changing only those word lines which are connected to the normal row decoders from an active state to a standby state based on a decision output of the decision means when the decision means has determined to select a memory cell belonging to the redundant row at a time of changing the word lines connected to the normal row decoders from a standby state to an active state.
According to the second aspect of this invention, there is provided a semiconductor memory device having a memory cell array having a plurality of memory cells connected to respective word lines and data lines and having a redundant row of memory cells, for accessing any of the memory cells by changing an associated word line and associated data line from a standby state to an active state, which semiconductor memory device comprises a plurality of normal row decoders for decoding input row address data for specifying word lines when access is made to those of the memory cells which are other than the redundant row of memory cells, thereby selecting those word lines to which those memory cells that are other than the redundant row of memory cells are connected; a redundant row decoder for specifying that word line to which the redundant row of memory cells is connected when access is made to any memory cell which belongs to the redundant row; decision means for determining whether or not to select a memory cell belonging to the redundant row based on the input row address data and selecting the redundant row decoder at a time of selecting the memory cell belonging to the redundant row; first control means for rendering those word lines which are connected to the normal row decoders to a standby state or an active state, generating a first control signal for changing only the word lines connected to the normal row decoders from the active state to the standby state when the decision means has determined to select a memory cell belonging to the redundant row and a second control signal for changing the word lines connected to the redundant row decoder to the standby state or the active state, and supplying the first control signal to the normal row decoders and the second control signal to the redundant row decoder; and second control means for selecting one of the plurality of normal row decoders based on the input row address data and rendering the normal row decoders to a non-selected state when the decision means has determined to select a memory cell belonging to the redundant row.
The semiconductor memory device according to the second aspect of this invention may comprise third control means, instead of the first control means, for supplying the normal row decoders and the redundant row decoder with a third control signal for rendering those word lines which are connected to the normal row decoders and the redundant row decoder to a standby state or an active state, and supplying the normal row decoders with a fourth control signal for changing only the word lines connected to the normal row decoders from the active state to the standby state when the decision means has determined to select a memory cell belonging to the redundant row.
With the structures according to the first and second aspects of this invention and the modification of the second aspect, the control means changes only those word lines which are connected to the normal row decoders from the active state to the standby state based on the decision output of the decision means when the decision means has determined to select a memory cell belonging to the redundant row at the time of changing the word lines connected to the normal row decoders from the standby state to the active state. This can allow a target normal row decoder to be selected without waiting for the decision being made on whether or not to select a memory cell belonging to the redundant row. It is therefore possible to quickly select the word line that is connected to the target normal row decoder.
According to the third aspect of this invention, there is provided a semiconductor memory device comprising a node to be precharged to a predetermined level; normal row decoding means for discharging the node to select one of normal word lines when predetermined address data is input; and precharge means for precharging the node again when one of redundant word lines is selected.
In the semiconductor memory device according to the third aspect of the invention, the precharge means may have one precharge transistor which is enabled to set the node to a precharge potential when a precharge command (PC) is externally input or one of the redundant word lines is selected. In this case, the precharge means may have first and second precharge transistors such that the first precharge transistor is enabled to set the node to the precharge potential when the precharge command (PC) is externally input and the second precharge transistor is enabled to set the node to the precharge potential when one of the redundant word lines is selected.
According to the fourth aspect of this invention, there is provided a semiconductor memory device comprising normal row decoding means for activating a predetermined one of the normal word lines when predetermined address data is input; redundancy decision means for outputting a decision signal for selecting a predetermined one of the redundant word lines when the address data is input; and means for deactivating the activated normal word line based on the decision signal.
In the semiconductor memory device according to the fourth aspect of this invention, the redundancy decision means may output redundancy decision signals corresponding to a plurality of redundant word lines to a redundant row decoder; and the decision signal may be enabled when one of the redundancy decision signals is enabled.
In any of the semiconductor memory devices according to the third and fourth aspect of this invention and their modifications, sub word drivers may be respectively connected to the normal word lines and redundant word lines.
With the structures according to the third aspect of this invention and the modifications thereof, it is possible to select a target normal row decoder without waiting for the decision being made on whether or not to select a memory cell belonging to the redundant row. This can ensure fast selection of the word line that is connected to the target normal row decoder.
With the structures according to the fourth aspect of this invention and its modifications, even if selection of a normal word line is temporarily attempted, when a redundant word line is selected, the normal word line can be deactivated, so that no problem arises in the operation of selecting a word line.